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U3280M
Transponder Interface for Microcontroller
General Description
The U3280M IC is a transponder interface which enables contactless ID systems, remote control systems, tag and sensor applications. It is able to supply a microcontroller with power from an RF field via a LC-resonant circuit and it enables the controller for contactless bidirectional data communication via this RF field. It includes a power management which handles switching between magnetic field and battery power supply. To store permanent data like identifiercode and configuration data the U3280M includes a 512-bit EEPROM with an serial interface .
Features
D Contactless power supply and communication interface D Up to 10 kbaud data rate (R/O) D Power management for contactless- and battery power supply D Frequency range 100 to 150 kHz D 32 x 16-bit EEPROM D Two wire serial interface D Shift register supported Biphase and Manchester modulator stage D Reset I/O line D Field clock extractor D Field and gap detection output for wake up and data reception D Field modulator with energy-saving damping stage
Applications
D Overview - Access control - Telemetry - Wireless sensors Par example: D Wireless passive access and active alarm control for protection of valuables D Contactless position sensors for alignments of machines D Contactless status verification and/ or data readout from sensors
VBatt Sensors, keys, displays, actuators NRST VDD 512-bit EEPROM memory SDA SCL
Energy
U3280M Transponder interface
VField regulator Damping stage Coil 1 Rectifier Power management
Coil 2 Field/gap detect Data Clock extractor >1 _ Serial interface Biphase modulator
Low power microcontroller
VSS
FC
NGAP
MOD
Transmit data Receive data/ field detected Field clock
Figure 1. Block Diagram
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U3280M
Ordering Information
Extended Type Number U3280M-MFB U3280M-MFBG3 Package SSO16 SSO16 Tube Taped and reeled Remarks
Pin Description
Pin 1 VBatt VDD SCL NRST SDA VSS n.c. FC 1 2 3 4 5 6 7 8
16578
16 Coil 2 2 15 Coil 1 14 n.c. 13 n.c. 12 n.c. 11 n.c. 10 NGAP 9 MOD 3 4 5 6 7 8 9 10 15
Symbol VBatt VDD
SCL NRST SDA VSS n.c. FC MOD NGAP Coil 1
16
Figure 2. Pinning
Coil 2
Function Power supply voltage input to connect a battery Power supply voltage for the mC and EEPROM. At this pin a buffer capacitor (0.5... 10 mF) must be connected to buffer the voltage during field supply and to block the VDD of the mC. Serial clock line Reset line bidirectional Serial data line Circuit ground Not connected Field clock output of the front end clock extractor Modulation input Gap and field detect output Coil input 1. Pin to connect a resonant circuitry for communication and field supply Coil input 2, see above
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1
1.1
Functional Description
The Transponder Interface
An on-chip Biphase and Manchester modulator can be activated and controlled by the serial interface. If this modulator is used it modulates the serial data stream at the serial inputs SDA and SCL into a Biphase or Manchester coded signal for the damping stage.
The U3280M is a transponder interface IC which is able to operate microcontrollers wireless and battery-independent. Wireless data communication and power supply are handled via an electromagnetic field and the coil antenna of the transponder interface. The U3280M consists of a rectifier stage for the antenna, a power management to handle field and battery power supply, a damping modulator and a field-gap detection stage for contactless data communication, further a field clock extraction and an EEPROM are on the chip. The internal rectifier stage rectifies the AC from the LCresonant circuit at the coil inputs and supplies the U3280M device and an additional microcontroller device with power. It is also possible to supply the device via the VBatt input with DC from a battery. The power management handles switching between battery supply (VBatt pin) and field supply automatically. It switches to field supply if a field is applied at the coil and it switches back to battery if the field is removed. The voltage from the coil or the VBatt pin is output at the VDD pin to supply the microcontroller or any other suited device. At the VDD pin a capacitor must be connected to smooth and buffer the supply voltage. This capacitor is also necessary to buffer the supply voltage during the communication (damping and gaps in the field). For communication, the chip contains a damping stage and a gap-detect circuitry. By means of the damping stage the coil voltage can be modulated to transmit data via the field. It can be controlled with the modulator input (MOD pin) via the microcontroller. The gap-detection circuitry detects gaps in the field and outputs the gap/field signal at the gap-detect output (Pin NGAP). For the storage of data like keycodes, identifiers and configuration bits a 512-bit EEPROM is available on the chip. It can be read and written by the microcontroller via an I2C compatible two-wire serial interface. The serial interface, the EEPROM and the microcontroller are supplied with the voltage at the VDD pin. That means the microcontroller can read and write the EEPROM if the supply voltage at VDD is in the operating range of the IC. The U3280M has build in operating modes to support a wide range of applications. These modes can be activated via the serial interface with special mode control bytes. To support applications with battery supply only, the power management can be switched off by software to disable the automatic switching to field supply.
1.2
Modulation
The transponder interface can modulate the magnetic field by its damping stage to transmit data to a base station. It modulates the coil voltage by varying the coil's load. The modulator can be controlled via the MOD pin. A high level ("1" ) increases the current into the coil and damps the coil voltage. A low level ("0") decreases the current and increases the coil voltage. The modulator generates a voltage stroke of about 2 Vpp at the coil. A high level at the MOD pin makes the maximum of the field energy available at VDD. During a reset a high level at the MOD pin causes the optimum conditions for starting the device and charging the capacitor at VDD after the field is applied at the coil. Digital input to control the damping stage (MOD) MOD = 0: coil not damped Vcoil_peak = VDD x 2 + VCMS = VCU MOD = 1: coil damped Vcoil_peak = VDD x 2 = VCD VCMS = VCID: modulation voltage stroke @ coil inputs Note: IFfthe automatic power management is disabled, the internal front end VDD is limited at VDDC. In this case the value VDDC must be used in the above formula.
1.3
Field clock
The field clock extractor of the interface makes the field clock available for the microcontroller. It can be used to supply timer inputs to synchronize modulation and demodulation with the field clock.
1.4
Gap Detect
The transponder interface can also receive data. The base station modulates the data with short gaps in the field. The gap-detection circuit detects these gaps in the magnetic field and outputs the NGAP/field signal at the NGAP pin. A high level indicates that a field is applied at the coil and a low level indicates a gap or that the field is off. The microcontroller must demodulate the incoming data stream at one of its inputs.
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U3280M
1.5 U3280M Signals and Timing
MOD
VCU VCMS Coil inputs
14101
VCD
Figure 3. Modulation
Gap detection and battery to field switching
tFGAP1 VFDON
Coil inputs
tFGAP0
VFDOFF
1. edge used as wakeup signal
NGAP Field clock FC
Battery supply Battery supply
Power management
tBFS
Coil supply if automatically power management is enabled
tFBS
Figure 4. GAP and Modulation Timing
Digital output of the gap-detection stage (NGAP) NGAP = 0: gap detected / no field VCOIL_peak = VFDoff NGAP = 1: field detected VCOIL_peak = VFDon Note: No amplifier is used in the gap-detection stage. A digital Schmitt trigger evaluates the rectified and smoothed coil voltage.
management switches to field supply. The field-detection stage of the power management has lowpass characteristics to avoid generating of wake signals and unnecessary switching between battery and field supply in case of interferences at the coil inputs.
1.7
Power Supply
1.6
Wake-up Signal
The U9280M has a power management that handles two power supply sources. Normally the IC is supplied by a battery at the VBatt pin. If a magnetic field is applied at the LC-resonant circuit of the device the field detection circuit switches automatically from VBatt to field supply. The VDD pin is used to connect a capacitor to smooth the voltage from the rectifier and to buffer the power while the field is modulated by gaps and damping. The EEPROM and the connected controller always operate with the voltage at the VDD pin. Note: During field supply the maximum energy from the field is used if a high level is applied at the MOD input!
If a field is applied at the coil of the transponder interface the microcontroller can be woken up with the wake signal at the NGAP pin. For that purpose the NGAP pin must be connected to an interrupt input of the microcontroller. A high level at the NGAP output indicates an applied field and can be used as wake signal for the microcontroller via an interrupt. The wake signal is generated if the power
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1.7.1 Automatic Power Management
There are different conditions to switch from the battery to field and back from field to the battery. The power management switches from battery to field if the rectified voltage (Vcoil) from the coil inputs becomes higher than the field-on-detection voltage (VFDon), even if no battery voltage is available (0 < VBatt < 1.8 V). It switches back to battery if the coil voltage becomes lower than the field-off-detection voltage (VFDoff). The field detection stage of the power management has lowpass characteristics to suppress noise. An applied field needs a time delay tBFS (battery-to-field switch delay) to change the power supply. If the field is removed from the coil, the power management will generate a reset that can be connected to the microcontroller. VCoil u VFDon for t u tBFS lation and gaps in the field. The size of this capacitor depends on the application. It must be of a dimension so that during modulation and gaps the ripple on the supply voltage is in the range of 100 mV to 300 mV. During gaps and damping the capacitor is used to supply the device, that means the size of the capacitor depends on the length of the gaps and damping cycles. Example: for a supply current 350 mA, 200 mV ripple @ VDD No Field Supply During 250 ms 500 ms Necessary CB 470 nF 1000 nF
1.8
Serial Interface
The transponder interface has an I2C like serial interface to the microcontroller for read and write accesses to the EEPROM. In a special mode the serial interface can also be used to control the Biphase/ Manchester modulator or the power management of the U3280M. The serial interface of the U3280M device must be controlled by a master device (normally the microcontroller) which generates the serial clock and controls the access via the SCL and SDA line. SCL is used to clock the data in and out of the device. SDA is a bidirectional line and used to transfer data into and out of the device. The following protocol is used for the data transfers.
Battery supply (VBatt)
Field supply
VCoil t VFDoff for t u tBFS
Figure 5. Switch conditions for the power management
Note: The rectified supply voltage from the coil is limited to VDDC (2.9 V). During field supply the battery is switched off and VDD changes to VDDC.
1.8.1
Serial Protocol
D Data states on the SDA line changing only during SCL is low. D Changes in the SDA line while SCL is high will be interpreted as START or STOP condition. D A STOP condition is defined as high-to-low transition on the SDA line while the SCL line is high. D Each data transfer must be initialized with a START condition and terminated with a STOP condition. The START condition wakes the device from standby mode and the STOP condition returns the device to standby mode. D A receiving device generates an acknowledge (A) after the reception of each byte. For that the master device must generate an extra clock pulse. If the reception was successfull the receiving master or slave device pulls down the SDA line during that clock cycle. If in transmit mode an acknowledge is not detected (N) by the interface, it will terminate further data transmissions and will go into receive mode. A master device must finish its read operation by a not acknowledge and then issue a stop condition to place the device into a known state.
1.7.2
Controlling the Power Management via the Serial Interface
The automatic mode of the power management can be switched off and on by a command from the microcontroller. If the automatic mode is switched off the IC is always supplied by the battery up to the next power-on reset or to a switch on command. The power management-on and -off command must be transferred via the serial interface. If the power managment is switched off and the device is supplied from the battery it can communicate via the field without load the field. This mode can be used to realize applications with battery supply if the field is to weak to supply the IC with power.
1.7.3
Buffer Capacitor CB
The buffer capacitor connected at VDD is used to buffer the supply voltage for the microcontroller and the EEPROM during field supply. It smoothes the rectified AC from the coil and buffers the supply voltage during modu-
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U3280M
SCL
SDA Stand Start by condition Data valid Data Data/ change acknowledge valid Stop Stand- condition by
13884
Figure 6. Serial protocol
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EEPROM address A2 Mode control bits C1 C0 Read/NWrite R/NW Start A4 A3 A1 A0 Ackn
Control Byte Format
The control byte follows the start condition and consists of the 5-bit row address, 2 mode control bits and the read/not write bit.
Data Transfer Sequence
Start
Control byte
Ackn
Data byte
Ackn
Data byte
Ackn
Stop
D Before the start condition and after the stop condition the device is in standby mode and the SDA line is switched as input with pull-up resistor.
D The start condition follows a control byte that determines the following operation. Bit 0 of the control byte is used to control the following transfer direction. A "0" defines a write access and a "1" a read access.
rial interface. The two mode control bits C1 and C2 define in which order the accesses to the buffer are performed: High byte - low byte or low byte - high byte. The EEPROM supports also autoincrement and autodecrement read operations. After sending the start address with the corresponding mode consecutive memory cells can be read row by row without transmission of the row addresses. Two special control bytes allow to initialize the complete EEPROM with "0" or with "1".
1.9
EEPROM
The EEPROM has a size of 512 bit and is organized as 32 x 16 bit matrix. To read and write data to and from the EEPROM serial interface must be used. The interface supports one and two byte write accesses and one to n- byte read accesses to the EEPROM.
1.9.2
Write Operations
1.9.1
EEPROM - Operation Modes
The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the START condition followed by writing a write control byte and one or two data bytes from the master. It is complete with the STOP condition from the master after the acknowledge cycle. If the EEPROM receives the control byte it loads the addressed memory cell into a 16-bit read/write buffer. The following data bytes overwrites the buffer. The internal EEPROM programming cycle is started by a stop condition after the first or second data byte. During the programming cycle the addressed EEPROM cells are cleared and the contents of the buffer is written back to the into the EEPROM cells. The complete erase-write cycle takes about 10 ms.
The operating modes of the EEPROM are defined via the control byte. The control byte contains the row address, the mode control bits and the read/not-write bit, that is used to control the direction of the following transfer. A "0" defines a write access and a "1" a read access. The five address bits select one of the 32 rows of EEPROM memory to be accessed. For all accesses the complete16-bit word of the selected row is loaded into a buffer. The buffer must be read or overwritten via the se-
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Acknowledge polling If the EEPROM is busy with an internal write cycle all inputs are disabled and the EEPROM will not acknowledge until the write cycle is finished. This can be used to determine when the write cycle is complete. The master must perform acknowledge polling by sending a start condition Write One Data Byte followed by the control byte. If the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop condition or perform further acknowlege polling sequencies. If the cycle is complete, it returns an acknowledge and the master can then proceed with the next read or write cycle.
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Start Control byte A Data byte 1 A Stop
Write Two Data Bytes
Start
Control byte
A
Data byte 1
A
Data byte 2
A
Stop
Write Control Byte Only
Start
Control byte
A
Stop
A -> acknowledge
Write Control Bytes
MSB
LSB 0
Write low byte first
A4
A3
A2
A1
A0
C1 0
C0 1
R/NW
Row address
Byte order
LB(R) MSB
HB(R)
LSB 0
Write high byte first
A4
A3
A2
A1
A0
C1 1
C0 0
R/NW
Row address
Byte order
HB(R)
LB(R)
HB: high byte; LB: low byte; R: row address
1.9.3
Read Operations
The EEPROM allows byte-, word- and current address read operations. The read operations are initiated in the same way as write operations. Every read access is initiated by sending the start condition followed by the control byte which contains the address and the read mode. After the device receives a read command it returns an acknowledge, loads the addressed word into the read\write buffer and sends the selected data byte to the master. The master has to acknowledge the received byte if it wants
to proceed the read operation. If two bytes are read out from the buffer the device increments respectively decrements the word address automatically and loads the buffer with the next word. The read mode bits determines if the low or high byte is read first from the buffer and if the word address is incremented or decremented for the next read access. If the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The master can terminate the read operation after every byte by not responding with an acknowledge (N) and by issuing a stop condition.
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Read One Data Byte Read Control Bytes Read n Data Bytes Read Two Data Bytes
The EEPROM with the serial interface has ist own reset circuitry. In systems with microcontrollers that have their
1.9.4
U3280M
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HB: high byte; LB: low byte, R: row address
Byte order
Read high byte first, addr. decrement
Byte order
Read low byte first, address increment
A -> acknowledge, N -> no acknowledge
Start
Start
Start
Initilization after a Reset Condition
Control byte
Control byte
Control byte
A
A
A
HB(R)
LB(R)
Data byte 1
Data byte 1
Data byte 1
HB(R)
LB(R)
A4
A4
MSB
MSB
A
A
N
A3
A3
Stop
Row address
Row address
HB(R-1)
LB(R+1)
Data byte 2
Data byte 2
A2
A2
own reset circuitry for power-on reset , watchdog reset or brown-out reset, it may be necessary to bring the U3280M into a known state independent on the internal reset. This is performed by reading one byte without acknowledging and then generating a stop condition.
A1
A1
HB(R+1)
LB(R-1)
A
N
A0
A0
----
Stop
C1
C1
1
0
---
---
Data byte n
C0
C0
0
1
HB(R-n)
LB(R+n)
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R/NW R/NW LSB LSB 1 1 N HB(R+n) LB(R-n) Stop
U3280M
1.10 Special Modes
Control Byte 1100x111b 1101x111b 11xx0111b 11xx1111b xxxxx110b Description Biphase modulation Manchester modulation Switch power managment off -> disables switching from battery to field supply Switch power managment on -> enables automatical switching between battery and field supply Reserved
Data Transfer Sequence for Biphase and Manchester Modulation:
AAA A A A A A A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AA AA A A AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA
Start Control byte Ackn Bit 1 Bit 2 Bit 3 .............................. Bit n Stop
With special control bytes the serial interface can be used to control the modulator stage or the power management. The EEPROM access and the serial interface are disabled in these modes until to the next stop condition. If no start or stop condition is generated the SCL and SDA line can be used for the modulator stage. SCL is used for the modulator clock and SDA is used for the data. In that mode the same conditions for clock and data changing like in the normal are valid. The SCL and SDA line can be used for continuous bit transfers, an acknowledge cycle after 8 bits must not be generated. Note: After a reset of the microcontroller it is not sure that the transponder interface has been reset too. It could still be in a receive or transmit cycle. To place the serial interface of the device into a known state the miocrocontroller should read one byte from the device without acknowledge and then generate a stop condition.
1.12 Antenna
1.11 Power-On Reset, NRST
The U3280M transponder front end starts working with the applied field. For the digital circuits like EEPROM serial interface and registers there is a reset circuitry. A reset is generated by a power-on condition at VDD, by switching back from field to battery supply and if a low signal is applied at the NRST-pin. The NRST-pin is a bidirectional pin and can also be used as reset output to generate a reset for the microcontroller if the circuit switches over from field to battery supply. This sets the microcontroller in a well defined state after the uncertain power supply condition during switching.
For the transponder interface a coil must be used as antenna. Air and ferrite cored coils can be used. For battery-less operation the working distance resp. the minimum coupling factor of an application depends on the power consumption and on the size of the antennas of the IC and the base station. With a power consumption of 150 mA a minimum magnetic coupling factor below 0.5% is within reach. For applications with a higher power consumption the coupling factor must be increased. The Q-factor of the antenna coil should be in the range between 30 to 80 for read only application and below 40 for bidirectional read-write applications. The antenna coil must be connected together with a capacitor as a parallel LC resonant circuit to the COIL1 and COIL2 pins of the IC. The resonance frequency f0 of the antenna circuit should be in the range of 100 to 150 kHz. The right LC combination can be calculated with the following formula: 1 LA + 2 C A (2 p f 0 ) Note: The coil input stage requires a minimum capacitor of 1.8 nF.
COIL1 LA CA COIL1
Example: Antenna frequency: f0 = 125 kHz, capacitor: CA = 2.2 nF 1 a LA + + 737 mH 2 2.2 nF (2 p 125 kHz)
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2.1
Electrical Characteristics
Absolute Maximum Ratings
Parameters Symbol VDD, VBatt Value 0 V to +7.0 V with reverse protection 15 15
VSS -0.6 VIN VDD +0.6
Voltages are given relative to VSS . Supply voltage Max. current out of VSS pin Max. current into VBatt pin Input voltage (on any pin) Input/output clamp current (VSS > Vi/Vo > VDD) Min. ESD protection (100pF through 1.5kW) Operating-temperature range Storage-temperature range Soldering temperature (t 10 sec) Unit V mA mA V mA kV _C _C _C
VIN IIK / IOK TAMB TSTG TSD
+/- 15 +/-2 - 40 to + 85 - 40 to + 125 260
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of these specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize built-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. VDD).
2.2
DC Characteristics - Transponder Interface U3280M
Test Conditions / Pins Symbol VBatt VDDB VDDC VDD > 2.0 V IFi ISl VDD = 2.0 V VDD = 6.5 V VDD = 2.0 V VDD = 6.5 V VDD > 1.8 V VDD > 1.8 V IS = 0.5 mA, VBatt = 2 V IWR IWR IRdp IRdp VFDon VFDoff VSD 2.3 400 Min. 2.0 VBatt- VSD 2.9 40 Typ. Max. 6.5 Unit V V V mA mA mA mA mA mA V V mV
Supply voltage VDD = 1.8 to 6.5 V, VSS = 0 V, Tamb = -40_C to 85_C unless otherwise specified Parameters Power supply Operating voltage at VBatt Operating voltage at VDD during battery supply VDD-limiter voltage during coil supply Operating current during field supply Sleep current EEPROM Operating current during erase/write cycle Operating current during read cycle *) Power management Field-on detection voltage Field-off detection voltage Voltage drop at power-supply switch
2.6
3.2 80 0.4 500 1200 300 350 2.9 150
2.5 0.8
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DC Characteristics - Transponder Interface U3280M( continued)
Supply voltage VDD = 1.8 to 6.5 V, VSS = 0 V, Tamb = -40_C to 85_C unless otherwise specified Parameters Test Conditions / Pins Coil inputs Coil 1 and Coil 2 Coil input current Input capacitance Coil voltage stroke during VCU > 5V modulation Icoil = 3 to 20 mA Pin MOD Input LOW voltage Input LOW voltage Input leakage current Pin NGAP/ FC Output LOW current VDD = 2.0 V VOL = 0.2 VDD Output HIGH current VDD = 2.0 V VOH = 0.8 VDD Serial interface I/O pins SCL and SDA Input LOW voltage Input HIGH voltage Input leakage current Output LOW current VDD = 2.0 V VOL = 0.2 VDD VDD = 6.0 V Output HIGH current VDD = 2.0 V VOH = 0.8 VDD VDD = 6.0 V *) Peak current during 1/4 of read cycle Symbol ICI CIN VCMS Min. Typ. Max. 20 30 1.8 2.3 4.0 Unit mA pF V
VIL VIH IIleakage IOL IOH
VIH 0.8VDD 10 0.08 -0.06 0.2 -0.15
0.2 VDD VDD
V V nA mA mA
0.3 -0.25
VIL VIH IIleakage IOL
VIH 0.7 VDD 0.7 2.8 -0.5 -1.8 10 0.9 3.5 -0.6 -2.2
0.3 VDD VDD 1.1 4.2 -0.7 -2.6
V V nA mA mA mA mA
IOH
2.3
AC Characteristics - Transponder Interface U3280M
Test Conditions / Pins Symbol fSCL tLOW tHIGH tR tF tSUSTA tHDSTA tSUDAT tHDDAT tSUSTO tBUF tI tDH Min. 0 4.7 4.0 Typ. Max. 100 Unit kHz ms ms ns ns ms ms ns ns ms ms ns ns 11 (14)
Supply voltage VDD = 1.8 to 6.5 V, VSS = 0 V, Tamb = -40_C to 85_C unless otherwise specified Parameters Serial interface timing SCL clock frequency Clock low time Clock high time SDA and SCL rise time SDA and SCL fall time Start condition setup time Start condition hold time Data input setup time Data input hold time Stop condition setup time Bus free time Input filter time Data output hold time Rev.A2, 04-May-00
1000 300 4.7 4.0 250 0 4.7 4.7 300 100 1000
U3280M
AC Characteristics - Transponder Interface U3280M (continued)
Supply voltage VDD = 1.8 to 6.5 V, VSS = 0 V, Tamb = -40_C to 85_C unless otherwise specified Parameters Coil inputs Coil frequency Gap detection Delay field off to GAP = 0 Delay field on to GAP = 1 Power management Battery to field switch delay Field to battery switch delay EEPROM Endurance Data erase/ write cycle time Data retention time Power up to read operation Power up to write operation Reset Power-on reset NRST Test Conditions / Pins Symbol fCOIL VcoilGap < 0.7 VDC VcoilGap > 3 VDC TFGAP0 TFGAP1 tBFS VBatt = 6.5 V tFBS 5 10 Min. 100 10 1 Typ. 125 Max. 150 50 50 1000 30 Unit kHz ms ms ms ms
Erase/ write-cycles For 16 bits access Tamb = 25_C
ED tDEW tDR tPUR tPUw
500000 9 10 0.2 0.2 12
Cycles ms years ms ms
VDDrise = 0 to 2 V VIl < 0.2 VDD
trise tres
10 1
ms ms
600 500 VDD NRST tRESDEL
5.5 5 ms 5.0 VDD NRST tRESDEL
tRESDEL ( ms )
300 200 100 0 1 2 3 4 VDD ( V ) 5 6
tRESDEL ( ms )
400
4.5 4.0 3.5 3.0 2.5 1 2 3
4 VDD ( V )
5
6
Figure 7. Typical reset delay after switching VDD on
Figure 8. Typical reset delay after switching VDD on
12 (14)
Rev.A2, 04-May-00
U3280M
6 5 4 3 2 1 0
VDD ( V )
Figure 9. VDD rise time to ensure power-on reset
Package Information
Package SSO16
Dimensions in mm
5.00 max 5.00 4.80 1.40 0.2 0.25 0.635 4.45 16 9 0.25 0.10 3.95 max 5.2 4.8 6.2 5.8
Rev.A2, 04-May-00
CCCCCCCCCCC CCCCCCCCCCC CCCCCCCCCCC CCCCCCCCCCC CCCCCCCCCCC
Not allowed
0 2 4 6 8 10 trise ( ms ) 12 14
technical drawings according to DIN specifications 13045
1
8
13 (14)
U3280M
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
1.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
14 (14)
Rev.A2, 04-May-00

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